Transconductance amplifier based on self-biased cascode structure

A transconductance amplifier based on a self-biased cascode structure, comprising a self-biased cascode input-stage structure constituted by NMOS input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by PMOS transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function, wherein:

• sources of the NMOS input transistors M1 and M2 are grounded;
• gates of the NMOS input transistors M1 and M3 are connected to an input signal VIN;
• gates of the NMOS input transistors M2 and M4 are connected to an input signal VIP;
• a drain of the NMOS input transistor M1 is connected to a source of the NMOS input transistor M3;
• a drain of the NMOS input transistor M2 is connected to a source of the NMOS input transistor M4;
• substrates of the NMOS input transistors M3 and M4 are connected to a bias voltage Vn;
• and the bias voltage Vn is provided by a gate voltage of the NMOS transistor M11 of which a gate and a drain are connected in an amplifier bias circuit;
• a gate and a drain of the PMOS transistor M5 are both connected to gates of the PMOS transistors M6, M7 and M8 and a drain of the NMOS input transistor M3;
• a drain of the PMOS transistor M6 is connected to a drain of the NMOS input transistor M4;
• a source of the PMOS transistor M5 is connected to a drain of the PMOS transistor M7;
• a source of the PMOS transistor M6 is connected to a drain of the PMOS transistor M8;
• sources of the PMOS transistors M7 and M8 are connected to a drain of the PMOS transistor M0;
• substrates of the PMOS transistors M5 and M6 are connected to a bias voltage Vp;
• and the bias voltage Vp is provided by a gate voltage of the PMOS transistor M13 of which a gate and a drain are connected in the amplifier bias circuit;
• a source of the PMOS transistor M10 is connected to a supply voltage vdd;
• a drain of the PMOS transistor M10, one end of the compensation capacitor Cc, a drain of the NMOS transistor M9 and one end of the load capacitor CL are connected to form a connection node;
• the connection node is an output end Vout of the transconductance amplifier;
• a gate of the PMOS transistor M10 is connected to a drain of the NMOS input transistor M4;
• the other end of the compensation capacitor Cc is connected to a drain of the PMOS input transistor M2;
• the other end of the load capacitor CL and a source of the NMOS transistor M9 are grounded;
• and a gate of the NMOS transistor M9 is connected to a gate of the NMOS transistor M12;
• and
• sources of the PMOS transistors M0 and M13 are connected to the supply voltage vdd;
• a gate of the PMOS transistor M0 is connected to a gate and a drain of the PMOS transistor M13;
• a drain of the PMOS transistor M13 is connected to a drain of the NMOS transistor M12;
• a gate of the NMOS transistor M12 is connected to one end of the reference current source Iref and a gate and a drain of the NMOS transistor M11;
• sources of the NMOS transistors M11 and M12 are grounded;
• and the other end of the reference current source Iref is connected to the supply voltage vdd.