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US 11,120,846 B2Granted
Sense amplifier based flip-flop capable of resolving metastable state by removing unintentional current from output nodes
AssigneeSK hynix Inc.
InventorsSungWoo Kim, InHwa Jung
Life of this patent
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Abstract
A semiconductor integrated circuit includes a sense amplifier circuit suitable for generating differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and outputting the differential output signals to first and second nodes, respectively, a latch circuit suitable for feeding back and latching the differential output signals between the first and second nodes, and a control circuit suitable for controlling the feedback of the differential output signals between the first and second nodes in response to an initialization signal.
Claims17
A semiconductor integrated circuit comprising:
- a sense amplifier circuit configured to generate differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and output the differential output signals to first and second nodes, respectively;
- a latch circuit configured to feedback and latch the differential output signals between the first and second nodes;
- a control circuit configured to control the feedback of the differential output signals between the first and second nodes in response to an initialization signal;
- and
- a reset circuit configured to fix an initial value of the clock signal by resetting the clock signal in response to the initialization signal, and output the reset clock signal to the sense amplifier circuit,
- wherein the control circuit controls the feedback by blocking the feedback of the differential output signals from the second node to the first node.
3 more elements
A semiconductor integrated circuit comprising:
- a reset circuit configured to fix an initial value of a clock signal by resetting the clock signal in response to an initialization signal which is activated to a logic low level within an initial operation period;
- a sense amplifier circuit configured to generate differential output signals by sensing and amplifying a level difference of differential input signals in response to the reset clock signal, and output the generated differential output signals to first and second nodes, respectively;
- a latch circuit configured to feedback and latch the differential output signals between the first and second nodes;
- and
- a control circuit configured to block the feedback of the differential output signals from the second node to the first node, in response to the initialization signal.
2 more elements
A flip-flop comprising:
- a sense amplifier circuit configured to generate differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and output the differential output signals to first and second nodes, respectively;
- a latch circuit including first and second inverters which are coupled in a form of an inverter chain between the first and second nodes, and configured to latch the differential output signals;
- a first NMOS transistor coupled between the first inverter and a terminal of a ground voltage, and configured to receive a power supply voltage through a gate thereof;
- a second NMOS transistor coupled between the second inverter and the terminal of the ground voltage, and configured to receive an initialization signal through a gate thereof;
- and
- a reset circuit configured to fix an initial value of the clock signal by resetting the clock signal in response to the initialization signal, and output the reset clock signal to the sense amplifier circuit,
- wherein the initialization signal is activated to a logic low level within an initial operation period of the flip-flop.
4 more elements
An integrated circuit comprising:
- a differential amplifier configured to amplify differential signals from first and second input nodes and output amplified differential signals to first and second output nodes, respectively;
- a latch configured to feedback and latch the amplified differential signals between the first and second output nodes;
- a precharger configured to precharge the first output node to a logic high level in response to a control signal enabled at an initial operation of the amplifier;
- a blocking circuit configured to block the feedback of the amplified differential signals from the second output node to the first output node in response to the control signal;
- and
- a reset circuit configured to fix an initial value of a clock signal by resetting the clock signal in response to an initialization signal, and output the reset clock signal to the differential sense amplifier circuit.
3 more elements
Dependencies are inferred from the claim text.