Image sensor with A/D conversion circuit having reduced DNL deterioration

A semiconductor device comprising:

• a reference voltage generation circuit for generating a reference voltage linearly varying with passage of time;
• a counter circuit for generating a lower bit counter signal and an upper bit counter signal each of which has a value varying with the passage of time and each of which includes a plurality of bit counter signals;
• and
• an integration type A/D converter circuit including
• a comparator circuit for comparing an input signal with the reference voltage and outputting a lower bit latch signal when the input signal and the reference voltage reach a predetermined relationship,
• a lower bit latch circuit for latching the lower bit counter signal in response to the lower bit latch signal,
• a determination circuit for outputting an upper bit latch signal in a period excluding an indefinite period in which the upper bit counter signal becomes indefinite based on the lower bit latch signal and a predetermined bit counter signal in the lower bit counter signal, and
• an upper bit latch circuit for latching the upper bit counter signal in response to the upper bit latch signal, wherein the upper bit counter signal latched in the upper bit latch circuit and the lower bit counter signal latched in the lower bit latch circuit are outputted as a digital signal corresponding to the input signal.

A system comprising:

• a plurality of photosensitive elements arranged in a matrix;
• a pixel portion having a plurality of signal lines arranged along a column of photosensitive elements arranged in a matrix, and coupled with photosensitive elements arranged in each column;
• a reference voltage generation circuit for generating a reference voltage linearly varying with passage of time;
• a counter circuit for outputting an upper bit counter signal and a lower bit counter signal each including a plurality of bit counter signals;
• a plurality of counter signal lines, arranged along row of the photosensitive elements arranged in the matrix, for transmitting the upper bit counter signals and the lower bit counter signals;
• and
• column converter unit, arranged along each column direction, having a plurality of signal lines arranged in each column and a plurality of integration type A/D converters arranged in each column;
• wherein each of the plurality of integration type A/D converters includes a comparator outputs a lower bit latch signal comparing an input signal supplied from a corresponding signal line with the reference voltage,
• a lower bit latch circuit latches lower bit counter signal transmitted from a counter signal line in response to the lower bit latch signal,
• a determination circuit outputs an upper bit latch signal in a period excluding an indefinite period in which an upper bit latch signal becomes indefinite based on the lower bit latch signal and a predetermined bit counter signal in the lower bit counter signal, and
• an upper bit latch circuit latches an upper bit counter signal transmitted from a counter signal line in response to the upper bit latch signal.