Methods and apparatus for performing clock and data duty cycle correction in a high-speed link

A method of operating an integrated circuit, the method comprising:

• with a serializer in the integrated circuit, receiving a clock signal;
• with transmit data path circuitry in the integrated circuit, receiving data signals from the serializer and generating corresponding output data;
• with a calibration circuit in the integrated circuit, receiving the output data from the transmit data path circuitry;
• with the calibration circuit, generating a clock duty cycle correction signal that mitigates clock duty cycle distortion in the output data;
• with the calibration circuit, generating a data duty cycle correction signal that mitigates data duty cycle distortion in the output data, wherein the data duty cycle correction signal is different than the clock duty cycle correction signal;
• with the calibration circuit, configuring the serializer to send a first test pattern to the transmit data path circuitry;
• and
• while the serializer is sending the first test pattern, sweeping only the clock duty cycle correction signal but not the data duty cycle correction signal until a comparator within the calibration circuit flips to determine a first code.

Transmit circuitry, comprising:

• a serializer circuit;
• a pre-driver circuit configured to receive signals from the serializer circuit;
• an output driver configured to receive signals from the pre-driver circuit;
• a clock duty cycle correction circuit configured to output a clock signal to the serializer circuit;
• and
• a calibration circuit configured to receive output signals from the output driver and to generate a clock duty cycle correction signal that controls the clock duty cycle correction circuit and a data duty cycle correction signal that controls the pre-driver circuit, wherein the calibration circuit comprises a detector and a control circuit, wherein the detector comprises an input polarity multiplexer, and wherein the control circuit is configured to generate a control signal that selectively inverts a polarity of the input polarity multiplexer.