Error correction decoder and memory system having the same

A memory system, comprising:

• a memory device;
• and
• a memory controller including a processor configured to receive read values from the memory device and perform error correction decoding based on an iterative decoding scheme based on the received read values,
• wherein the processor comprises:
• a memory configured to store a hard decision value of a variable node;
• a flipping function value generator configured to generate, in an i-th iteration, a first value based on a difference between a number of unsatisfied check nodes (UCNs) corresponding to the variable node and a number of satisfied check nodes (SCNs) corresponding to the variable node, and generate a flipping function value by selectively updating the first value based on a comparison of the first value to a reference value;
• and
• a comparator configured to output, in the i-th iteration, a signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on a comparison between the flipping function value and a flipping threshold value.