Method and apparatus for encoding and decoding data in memory system

A method for preforming an error correction in a memory system, the method comprising:

• generating syndromes based on a Bose-Chaudhuri-Hocquenghem (BCH) encoded word stored in the memory system;
• performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients;
• performing a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) circuit to generate error bits and iteration information;
• reordering the error bits to be sequential based on the iteration information;
• and
• performing the error correction on data of the BCH encoded word using the reordered error bits,
• wherein the FFT circuit includes a first FFT stage iteration operating on the ELP coefficients and the iteration information is generated from an output of a counter incremented for each iteration of the first FFT stage.

A decoding circuit for performing an error correction in a memory system, the decoding circuit comprising:

• a Bose-Chaudhuri-Hocquenghem (BCH) decoder comprising:
• a Syndrome stage for generating syndromes based on a BCH encoded Word stored in the memory system;
• a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients;
• a first Fast Fourier Transform (FFT) stage iteratively performing a first FFT operation on the ELP coefficients to generate first results;
• a second FFT stage iteratively performing a second FFT operation on the first results to generate second results;
• and
• a logic circuit configured to generate error bits from the second results, generate iteration information from an output of a counter incremented for each iteration of the first FFT stage, and reorder the error bits based on the iteration information,
• wherein the BCH decoder performs the error correction on data of the BCH encoded word using the reordered error bits.