Filter apparatus and control method

A method comprising:

• configuring an analog-to-digital converter to operate in a testing mode;
• configuring a filter to receive a stream of bits generated by the analog-to-digital converter, and accumulate values of the stream of bits until the number of clock cycles reaches a predetermined reference value, wherein an output signal of the filter is increased by 1 in response to a digital bit of 1 from the stream of bits, and the output signal of the filter is decreased by 1 in response to a digital bit of 0 from the stream of bits;
• and
• transferring the output signal of the filter into a result register.

A system comprising:

• a delta-sigma analog-to-digital converter having inputs coupled to a digital sensor;
• a digital logic circuit having an input connected to the delta-sigma analog-to-digital converter, the digital logic circuit being configured to process an output signal of the delta-sigma analog-to-digital converter during a normal operation mode;
• and
• a testing circuit comprising a filter configured to receive a first stream of digital bits from an output of the delta-sigma analog-to-digital converter, and apply an integration process to the first stream of digital bits to generate a second stream of digital bits, wherein a sample rate of the second stream of digital bits is a fraction of a sample rate of the first stream of digital bits, and wherein in the integration process, the filter keeps accumulating values of the first stream of digital bits until the number of clock cycles reaches a predetermined reference value.