Semiconductor devices

A semiconductor device, comprising:

• first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively, for N being an odd number of three or more;
• a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal;
• and
• a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal,
• wherein the filter circuit comprises:
• a first filter to which the majority clock signal is provided;
• a second inverter to which an output signal of the first filter is provided;
• and
• a second filter to which an output signal of the second inverter is provided,
• wherein the first filter is configured to output a clock signal with a duty ratio different from that of the majority clock signal, and
• wherein the first filter and the second filter have the same configuration.

A semiconductor device, comprising:

• first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively, for N being an odd number of three or more;
• a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal;
• and
• a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal,
• wherein the filter circuit comprises:
• a first filter to which the majority clock signal is provided;
• a second inverter to which an output signal of the first filter is provided;
• and
• a second filter to which an output signal of the second inverter is provided,
• wherein the first filter comprises:
• a third inverter to which the majority clock signal is provided;
• a first RS flipflop;
• and
• a first delay circuit that supplies a first delay signal to a set terminal of the first RS flipflop, the first delay signal being generated by delaying the majority clock signal;
• wherein the second filter comprises:
• a fourth inverter to which an output signal of the second inverter is provided;
• a second RS flipflop;
• and
• a second delay circuit that supplies a second delay signal to a set terminal of the second RS flipflop, the second delay signal being generated by delaying the output signal of the second inverter.