US 11,115,034 B2Granted

Signal detection circuit and signal detection method

AssigneeRealtek Semiconductor Corp.

InventorBing-Hung Chen

Life of this patent

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Abstract

The present invention provides a signal detection circuit, wherein the signal detection circuit includes a sampling circuit and a determination circuit. In the operations of the signal detection circuit, the sampling circuit uses a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal. The determination circuit refers to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip includes the signal detection circuit.

Claims15

Dependent claims

A signal detection circuit, comprising:

a sampling circuit, configured to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal;
and
a determination circuit, coupled to the sampling circuit, configured to refer to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip comprises the signal detection circuit;
a clock signal generating circuit, configured to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

1 more element

A signal detection method, comprising:

using a sampling circuit to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal;
and
referring to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip;
using a clock signal generating circuit to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 16/993,275Filed 14 Aug 2020
Priority: TW 10813485726 Sep 2019
Published: US 2021/0099179 A11 Apr 2021
Granted: 7 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03L 7/091
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…
H03K 3/356
By the use, as active elements, of field-effect transistors with internal or external positive feedback: bistable circuits
H03L 7/0807
Details of the phase-locked loop: concerning mainly a recovery circuit for the reference signal
H03L 7/183
Using a frequency divider or counter in the loop: a time difference being used for locking the loop, the counter counting between fixed numbers or…

Family

US 2021/0099179 A1Pre-grant publication · published 1 Apr 2021
US 11,115,034 B2This patent

From the US filing history. Foreign family members aren’t listed.

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