PLL system and device with a low noise charge pump

A phase locked loop system comprising:

• a phase frequency detector (PFD) providing a shifted UP pulse swinging between a first low voltage and a first high voltage;
• and
• a first charge pump (CP) comprising a set of switching transistors and a set of constant gate bias transistors, in that the set of switching transistors are rated with a first breakdown voltage and a first switching speed, and the set of constant gate bias transistors are rated at a second breakdown voltage and a second switching speed, in that, the first breakdown voltage is substantially half the second breakdown voltage and the first switching speed is greater than the second switching speed,
• wherein the PFD is coupled to the CP such that, the shifted UP pulse drives a first switching transistors in the set of switching transistors to provide a high voltage capable signal at an output terminal through a first constant bias transistor, in the set of constant gate bias transistors, that is biased for charge pump.