Integrated circuit, test method for testing integrated circuit, and electronic device

An integrated circuit comprising:

• a first logic circuit configured to first implement logic information;
• and
• a first switch circuit configured to enable switching of wiring lines connected to the first logic circuit,
• the first logic circuit comprising:
• a first memory;
• a first look-up table circuit having a first output terminal for outputting data stored in the first memory based on a first input signal;
• a first selection circuit having a first input terminal to which the first output terminal is connected, a second input terminal that receives scan input data, and a second output terminal, the first selection circuit being configured to select one of the first input terminal and the second input terminal based on a scan enable signal and connect selected one of the first input terminal and the second input terminal to the second output terminal;
• a first flip-flop having a third input terminal connected to the second output terminal and a third output terminal;
• and
• a second selection circuit having a fourth input terminal connected to the third output terminal, a fifth input terminal connected to the first output terminal, and a fourth output terminal, the second selection circuit being configured to select one of the fourth input terminal and the fifth input terminal based on an enable signal and connect selected one of the fourth input terminal and the fifth input terminal to the fourth output terminal,
• the first switch circuit performing the switching of the wiring lines in response to signals from the third output terminal and the fourth output terminal.