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US 11,115,022 B2Granted
System and method for integrated circuit usage tracking circuit with fast tracking time for hardware security and re-configurability
AssigneeNorthwestern University
InventorJie Gu
Life of this patent
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Abstract
An accelerated aging circuit is described to shorten the required stress time to a few seconds of operation. Due to the challenges posed by process variation in advanced CMOS technology, a stochastic processing methodology is also described to reduce the failure rate of the tracking and detection. Combining both circuit and system level acceleration, the creation of a silicon marker can be realized within seconds of usage in contrast with days of operation from previously reported aging monitor.
Claims17
A system, comprising:
- an aging accelerating circuit, the aging accelerating circuit to create a silicon marker during real-time operation to aid in determining a usage of a chip, wherein the aging accelerating circuit comprises a target aging transistor and supportive transistors, wherein the supportive transistors comprise transmission gates coupled to the target aging transistor, wherein, during a stress phase of the aging accelerating circuit, the transmission gates are configured to isolate the target aging transistor from the supportive transistors and the supportive transistors are configured to operate without overstress wherein the aging accelerating circuit transitions from the stress phase to a comparison phase, and enters a sleep phase after the comparison phase to provide aging protection to the aging accelerating circuit.
A method comprising:
- creating a silicon marker to determine aging of stressed chips during real-time operation within only a few seconds of operation;
- providing, during a stress phase when determining aging of the stressed chips, an elevated target voltage to an age accelerating circuit, wherein the age accelerating circuit comprises a target aging transistor and supportive transistors, wherein the supportive transistors comprise transmission gates coupled to the target aging transistor, wherein, during the stress phase, the transmission gates are configured to isolate the target aging transistor from the supportive transistors and the supportive transistors are configured to operate without overstress, wherein the aging accelerating circuit transitions from the stress phase to a comparison phase, and enters a sleep phase after the comparison phase to provide aging protection to the aging accelerating circuit;
- and
- performing stochastic processing to ensure a detection accuracy of stressed chips within tolerance to process variation.
1 more element
Dependencies are inferred from the claim text.