Impedance calibration circuit and memory device including the same

An impedance calibration circuit comprising:

• a first code generation circuit configured to:
• generate a first code by using a first reference resistor, and
• form a resistance based on the first reference resistor and the first code;
• a second code generation circuit including a plurality of ZQ pull-up drivers configured to form a resistance of a second reference resistor, based on the first code, the second code generation circuit configured to generate a second code by using the second reference resistor;
• and
• a target impedance code generation circuit configured to:
• select one from among the first code and the second code according to a result of comparing a target impedance value with a threshold impedance value,
• generate a target impedance code based on using the selected code, and
• form an impedance having the target impedance value for a termination driver connected to the impedance calibration circuit,
• wherein each ZQ pull-up driver includes either one or more PMOS transistors or one or more NMOS transistors.

An impedance calibration method performed by an impedance calibration circuit in a memory device comprising a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, the impedance calibration circuit connected to a first reference resistor, the impedance calibration method comprising:

• generating a first code for forming a resistance based on the first reference resistor, by using the first reference resistor;
• generating a second code for forming a resistance of a second reference resistor formed based on the first code, by using the second reference resistor;
• and
• generating a target impedance code corresponding to a target impedance value, based on the first code, the second code, and the target impedance value.