Device including multi-mode input pad
AssigneeSkyworks Solutions, Inc.
InventorsBo Zhou, Guillaume Alexandre Blin
Life of this patent
Estimating the term…
Abstract
A circuit component has an address determined from a voltage level applied to a single electrical contact of the circuit component. The circuit component is configured to be assigned one of at least three unique addresses and to select from among the at least three unique addresses based on the voltage level.
Claims15
A circuit component having a multi-bit binary address, the multi-bit binary address determined from a voltage level applied to a single electrical contact of the circuit component, the circuit component configured to be assigned one of at least three unique multi-bit binary addresses and to select from among the at least three unique multi-bit binary addresses based on the voltage level, the multi-bit binary address assuming a first value responsive to the voltage level being a first voltage level, a second value responsive to the voltage level being a second voltage level, and a third value responsive to the voltage level being a floating voltage level between the first voltage level and the second voltage level, the circuit component further configured to be connected to a clock signal line and a data signal line in an electronic device along with at least two other substantially identical circuit components also configured to be connected to the clock signal line and the data signal line, each of the circuit component and the at least two other substantially identical circuit components having a unique multi-bit binary address selected from among the at least three unique multi-bit binary addresses.
An electronic device comprising:
- a master circuit component;
- and
- a plurality of secondary circuit components, each of the plurality of secondary circuit components configured to be assigned a unique multi-bit binary address selected from among at least three unique multi-bit binary addresses by application of a voltage to a single electrical contact of each respective one of the plurality of secondary circuit components, different levels of the voltage applied to the single electrical contact being associated with different unique multi-bit binary addresses, the master circuit configured to define a particular one of the plurality of secondary circuit components to communicate with by transmitting one of the unique multi-bit binary addresses over a signal line electrically coupled to a communication interface in each of the plurality of secondary circuit components,
- wherein the master circuit component and the plurality of secondary circuit components communicate via a serial bus protocol including a clock signal line and a single data line,
- the electronic device being included in a radio frequency device.
A circuit component having a multi-bit binary address, the multi-bit binary address determined from a voltage level applied to a single electrical contact of the circuit component, the circuit component having electronic circuitry configured to determine the multi-bit binary address from the voltage level applied to the single electrical contact, the electronic circuitry including a voltage divider and a plurality of comparators, the single electrical contact in electrical contact with an input of each of the plurality of comparators, the circuit component configured to be assigned one of at least three unique multi-bit binary addresses and to select from among the at least three unique multi-bit binary addresses based on the voltage level, the circuit component further configured to be connected to a clock signal line and a data signal line in an electronic device along with at least two other substantially identical circuit components also configured to be connected to the clock signal line and the data signal line, each of the circuit component and the at least two other substantially identical circuit components having a unique multi-bit binary address selected from among the at least three unique multi-bit binary addresses.
Dependencies are inferred from the claim text.