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US 11,115,008 B2Granted
Single event upset-tolerant latch circuit and flip-flop circuit
AssigneesJapan Aerospace Exploration Agency, High-Reliability Engineering & Components Corporation
InventorsAkifumi Maru, Satoshi Kuboyama, Tsukasa Ebihara, Akiko Makihara
Life of this patent
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Abstract
Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.
Claims12
A single event upset-tolerant latch circuit configured such that four Dual Interlocked Storage Cell (DICE) elements are connected in series and in a loop configuration, each of the DICE elements being comprised of a p-type transistor and an n-type transistor, wherein a gate terminal in each one of the p-type and n-type transistors and a drain terminal in the other are mutually connected, each of the DICE elements having a first node Interconnecting between the gate terminal of the p-type transistor and the drain terminal of the n-type transistor, and a second node interconnecting between the drain terminal of the p-type transistor and the gate terminal of the n-type transistor, the single event upset-tolerant latch circuit comprising:
- a first DICE element comprised of a first p-type transistor (P1_1) and a first n-type transistor (N1_1), wherein a gate terminal in each one of the first p-type and n-type transistors and a drain terminal in the other are mutually connected;
- a second DICE element comprised of a second p-type transistor (P2_1) and a second n-type transistor (N2_1), wherein a gate terminal in each one of the second p-type and n-type transistors and a drain terminal in the other are mutually connected;
- a third DICE element comprised of a third p-type transistor (P3_1) and a third n-type transistor (N3_1), wherein a gate terminal in each one of the third p-type and n-type transistors and a drain terminal in the other are mutually connected;
- and
- a fourth DICE element comprised of a fourth p-type transistor (P4_1) and a fourth n-type transistor (N4_1), wherein a gate terminal in each one of the fourth p-type and n-type transistors and a drain terminal in the other are mutually connected;
- wherein:
- a node interconnecting between a gate terminal of a p-type transistor comprised in the first DICE element and a drain terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's first node;
- a node interconnecting between a gate terminal of a p-type transistor comprised in the second DICE element and a drain terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's first node;
- a node interconnecting between a gate terminal of a p-type transistor comprised in the third DICE element and a drain terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's first node;
- a node interconnecting between a gate terminal of a p-type transistor comprised in the fourth DICE element and a drain terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's first node;
- a node interconnecting between a drain terminal of a p-type transistor comprised in the first DICE element and a gate terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's second node;
- a node interconnecting between a drain terminal of a p-type transistor comprised in the second DICE element and a gate terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's second node;
- a node interconnecting between a drain terminal of a p-type transistor comprised in the third DICE element and a gate terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's second node;
- and
- a node interconnecting between a drain terminal of a p-type transistor comprised in the fourth DICE element and a gate terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's second node;
- and wherein:
- the first DICE element's first node is connected to the fourth DICE element's second node;
- the second DICE element's first node is connected to the first DICE element's second node;
- the third DICE element's first node is connected to the second DICE element's second node;
- and
- the fourth DICE element's first node is connected to the third DICE element's second node;
- and wherein:
- the second DICE element's first node and the fourth DICE element's first node are connected, respectively, to a first data input part and a second data input part each configured such that a conduction state thereof is controlled by control of a clock;
- and
- at least one of the first DICE element's second node, the second DICE element's second node, the third DICE element's second node and the fourth DICE element's second node is connected to a data output part;
- and wherein:
- each of the first p-type transistor (P1_1), the first n-type transistor (N1_1), the second p-type transistor (P2_1), the second n-type transistor (N2_1), the third p-type transistor (P3_1), the third n-type transistor (N3_1), the fourth p-type transistor (P4_1) and the fourth n-type transistor (N4_1) is configured such that three transistors for redundancy are added thereto at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel;
- and
- each of the first data input part and the second data input part is made dually redundant.
26 more elements
A single event upset-tolerant flip-flop circuit comprising a front-stage master part and a rear-stage slave part each comprising a single event upset-tolerant latch circuit, wherein
- an output of the single event upset-tolerant latch circuit in the master part is connected to an input of the single event upset-tolerant latch circuit in the slave part, and
- a clock having a phase reverse to that of a clock to be input to the single event upset-tolerant latch circuit in the master part is input to the single event upset-tolerant latch circuit in the slave part, wherein the single event upset-tolerant latch circuit is configured such that four Dual Interlocked Storage Cell (DICE) elements are connected in series and in a loop configuration, each of the DICE elements being comprised of a p-type transistor and an n-type transistor, wherein a gate terminal in each one of the p-type and n-type transistors and a drain terminal in the other are mutually connected, each of the DICE elements having a first node interconnecting between the gate terminal of the p-type transistor and the drain terminal of the n-type transistor, and a second node interconnecting between the drain terminal of the p-type transistor and the gate terminal of the n-type transistor, the single event upset-tolerant latch circuit comprising:
- a first DICE element comprised of a first p-type transistor (P1_1) and a first n-type transistor (N1_1), wherein a gate terminal in each one of the first p-type and n-type transistors and a drain terminal in the other are mutually connected;
- a second DICE element comprised of a second p-type transistor (P2_1) and a second n-type transistor (N2_1), wherein a gate terminal in each one of the second p-type and n-type transistors and a drain terminal in the other are mutually connected;
- a third DICE element comprised of a third p-type transistor (P3_1) and a third n-type transistor (N3_1), wherein a gate terminal in each one of the third p-type and n-type transistors and a drain terminal in the other are mutually connected;
- and
- a fourth DICE element comprised of a fourth p-type transistor P4_1) and a fourth n-type transistor (N4_1), wherein a gate terminal in each one of the fourth p-type and n-type transistors and a drain terminal in the other are mutually connected;
- wherein:
- a node interconnecting between a gate terminal of a p-type transistor comprised in the first DICE element and a drain terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's first node;
- a node interconnecting between a gate terminal of a p-type transistor comprised in the second DICE element and a drain terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's first node;
- a node interconnecting between a gate terminal of a p-type transistor comprised in the third DICE element and a drain terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's first node:
- a node interconnecting between a gate terminal of a p-type transistor comprised in the fourth DICE element and a drain terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's first node;
- a node interconnecting between a drain terminal of a p-type transistor comprised in the first DICE element and a gate terminal of an n-type transistor comprised in the first DICE element forms a first DICE element's second node;
- a node interconnecting between a drain terminal of a p-type transistor comprised in the second DICE element and a gate terminal of an n-type transistor comprised in the second DICE element forms a second DICE element's second node;
- a node interconnecting between a drain terminal of a p-type transistor comprised in the third DICE element and a gate terminal of an n-type transistor comprised in the third DICE element forms a third DICE element's second node;
- and
- a node interconnecting between a drain terminal of a p-type transistor comprised in the fourth DICE element and a gate terminal of an n-type transistor comprised in the fourth DICE element forms a fourth DICE element's second node;
- and wherein:
- the first DICE element's first node is connected to the fourth DICE element's second node;
- the second DICE element's first node is connected to the first DICE element's second node;
- the third DICE element's first node is connected to the second DICE element's second node;
- and
- the fourth DICE element's first node is connected to the third DICE element's second node;
- and wherein:
- the second DICE element's first node and the fourth DICE element's first node are connected, respectively, to a first data input part and a second data input part each configured such that a conduction state thereof is controlled by control of a clock;
- and
- at least one of the first DICE element's second node, the second DICE element's second node, the third DICE element's second node and the fourth DICE element's second node is connected to a data output part;
- and wherein:
- each of the first p-type transistor (P1_1), the first n-type transistor N1_1), the second p-type transistor (P2_1), the second n-type transistor (N2_1), the third p-type transistor (P3_1), the third n-type transistor (N3_1), the fourth p-type transistor (P4_1) and the fourth n-type transistor (N4_1) is configured such that three transistors for redundancy are added thereto at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel;
- and
- each of the first data input part and the second data input part is made dually redundant.
28 more elements
Dependencies are inferred from the claim text.