Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times

A method, comprising:

• receiving a clock signal at a clock generator circuit;
• providing, via a two-phase flip-flop of the clock generator circuit, both a first driver control signal and a second driver control signal directly responsive to the clock signal, wherein the first driver control signal and the second driver control signal are complementary;
• providing, via a first driver circuit of the clock generator circuit, a first output signal responsive to both of the first driver control signal and the second driver control signal, wherein providing the first output signal includes:
• driving, via a first passgate of the first driver circuit, the first output signal to a first logical value in response to the first and second control signals having first respective complementary values;
• and
• driving, via a second passgate of the first driver circuit, the first output signal to a second logical value in response to the first and second control signals having second respective complementary values, wherein the first passgate and the second passgate are each controlled by both of the first and second control signals;
• and
• providing, via a second driver circuit of the clock generator circuit that is coupled in parallel with the first driver circuit, a second output signal responsive to both of the first driver control signal and the second driver control signal, wherein the first output signal and the second output signal are complementary.

A method comprising:

• receiving a clock signal at a clock generator circuit;
• providing, via a two-phase flip-flop of the clock generator circuit, both a first driver control signal and a second driver control signal directly responsive to the clock signal, wherein the first driver control signal and the second driver control signal are complementary;
• providing, via a first driver circuit of the clock generator circuit, a first output signal responsive to both of the first driver control signal and the second driver control signal, wherein providing the first output signal includes:
• driving, via a first passgate of the first driver circuit, the first output signal to a first logical value in response to the first and second control signals having first respective complementary values;
• and
• driving, via a second passgate of the first driver circuit, the first output signal to a second logical value in response to the first and second control signals having second respective complementary values
• providing, via a second driver circuit of the clock generator circuit that is coupled in parallel with the first driver circuit, a second output signal responsive to both of the first driver control, signal and the second driver control signal, wherein the first output signal and the second output signal are complementary, wherein providing the second output signal includes:
• driving, via a third passgate of the second driver circuit, the second output signal to the second logical value in response to the first and second control signals having the first respective complementary values;
• and
• driving, via a fourth passgate of the second driver circuit, the second output signal to the first logical value in response to the first and second control signals having the second respective complementary values.