Electrostatic discharge protection circuit

An electrostatic discharge protection circuit comprising:

• an inverter formed between a first power line and a first ground line, and configured to operate in a range between a first power and a first ground;
• a level shift circuit formed between a second power line and a second ground line, and configured to operate in a range between a second power having a level higher than the first power and a second ground;
• a signal line connecting an output terminal of the inverter and an input terminal of the level shift circuit;
• a first protection circuit configured to form a first bypass path that bypasses a stress due to electrostatic discharge by a semiconductor device which has the same breakdown voltage as the inverter, between the signal line and the second ground line when the electrostatic discharge occurs at the output terminal of the inverter, to protect a semiconductor device of the level shift circuit;
• and
• a second protection circuit configured to form a second bypass path that bypasses a stress due to electrostatic discharge, between the signal line and the second ground line when the electrostatic discharge occurs at the input terminal of the level shift circuit, to protect the semiconductor device of the level shift circuit.