Semiconductor device and semiconductor device system

A semiconductor device system comprising:

• a semiconductor device including:
• an internal circuit region in which an internal circuit including a plurality of logic circuits and a plurality of analog circuits is formed;
• a peripheral I/O region formed around the internal circuit region;
• at least one of a first power supply cell and a second power supply cell, the first power supply cell formed in the peripheral I/O region and coupled to a first terminal, and the second power supply cell formed in the peripheral I/O region and coupled to a second terminal, wherein the first terminal is a high potential side terminal, and wherein the second terminal is a low potential side terminal;
• a voltage detection circuit configured to output a detection signal when a voltage between the first terminal and the second terminal reaches a predetermined voltage;
• a first amplifier circuit configured to amplify the detection signal and output a drive signal;
• a second amplifier circuit configured to feedback-amplify the detection signal;
• and
• a discharge element coupled between the first terminal and the second terminal and having a discharge capability depending on the drive signal,
• wherein the discharge element is a first PMOS transistor having a source coupled to the first terminal and a drain coupled to the second terminal,
• wherein the first amplifier circuit includes:
• a second PMOS transistor having a source coupled to the first terminal and a gate supplied with the detection signal;
• a first resistor having one end coupled to a drain of the second PMOS transistor and the other end coupled to the second terminal;
• and
• a first output circuit coupled to a connection node of the second PMOS transistor and the first resistor and configured to output the drive signal to a gate of the first PMOS transistor, and
• wherein the second amplifier circuit comprises:
• a third PMOS transistor having a source coupled to the first terminal and a gate supplied with the detection signal;
• a second resistor having one end coupled to a drain of the third PMOS transistor and the other end coupled to the second terminal;
• a second output circuit coupled to a connection node of the third PMOS transistor and the second resistor;
• and
• a fourth PMOS transistor having a gate supplied with an output signal of the second output circuit, a source coupled to the gate of the third PMOS transistor directly or through at least one of a plurality of rectifying elements of the voltage detection circuit, and a drain coupled to the second terminal directly or through at least one of the plurality of the rectifying elements.

A semiconductor device comprising:

• a voltage detection circuit configured to output a detection signal when a voltage between a first terminal and a second terminal reaches a predetermined voltage, wherein the first terminal is a high potential side terminal, and wherein the second terminal is a low potential side terminal;
• a first amplifier circuit having a first input node and a first output node, the first input node coupled to the voltage detection circuit and supplied with the detection signal, the first amplifier circuit amplifying a signal supplied to the first input node and output a drive signal from the first output node;
• a second amplifier circuit supplied with the detection signal, amplifying the detection signal, and outputting an amplified signal to the first input node;
• and
• a discharge element coupled between the first terminal and the second terminal and controlling a discharge current flowing between the first terminal and the second terminal based on the drive signal,
• wherein the discharge element comprises a first NMOS transistor having a source coupled to the second terminal and a drain coupled to the first terminal,
• wherein the first amplifier circuit comprises:
• a second NMOS transistor having a source coupled to the second terminal and a gate supplied with the detection signal;
• a first resistor having one end coupled to a drain of the second NMOS transistor and the other end coupled to the first terminal;
• and
• a first output circuit coupled to a connection node of the second NMOS transistor and the first resistor and configured to output the drive signal to a gate of the first NMOS transistor,
• wherein the second amplifier circuit comprises:
• a third NMOS transistor having a source coupled to the second terminal and a gate supplied with the detection signal;
• a second resistor having one end coupled to a drain of the third NMOS transistor and the other end coupled to the first terminal;
• a second output circuit coupled to a connection of the third NMOS transistor and the second resistor;
• and
• a fourth NMOS transistor having a gate supplied with an output signal of the second output circuit, a source coupled to the gate of the third NMOS transistor directly or through at least one of a plurality of rectifying elements of the voltage detection circuit, and a drain coupled to the first terminal directly or through at least one of the plurality of the rectifying elements,
• wherein the first amplifier circuit configured to output a first drive signal when the first input node is supplied with the detection signal, and to output a second drive signal when the first input node is supplied with the amplified signal of the second amplifier circuit, and
• wherein the discharge current based on the second drive signal is larger than the discharge current based on the first drive signal.