Process for fabricating resistive memory cells

A memory device, comprising:

• a substrate;
• a first conductive layer including a first electrode pad and a second electrode pad separated from the first electrode pad along a first direction, the first and second electrode pads each having a first side on the substrate, the first sides of each of the first and second electrode pads being rectangular;
• a band covering the first and second electrode pads, the band including a dielectric layer and a second conductive layer on the first and second electrode pads;
• a first memory cell including the first electrode pad, the dielectric layer, and the second conductive layer;
• a second memory cell including the second electrode pad, the dielectric layer, and the second conductive layer, wherein the first and second memory cells define a memory plane within an interconnect portion of the memory device, the memory plane including a plurality of memory cells extending in orthogonal first and second directions;
• word lines traversing the memory plane in the first direction;
• hit lines traversing the memory plane in the second direction;
• first electrically conductive contacts connecting the word lines to the first and second electrode pads;
• and
• a second electrically conductive contact connecting one of the bit lines to the second conductive layer.

An integrated circuit, comprising:

• a memory device having a first memory cell and a second memory cell, the memory device including:
• a first electrode pad;
• a second electrode pad spaced laterally apart from the first electrode pad;
• a dielectric layer covering the first and second electrode pads;
• and
• a third electrode on the dielectric layer and overlying the first and second electrode pads, wherein the first and second memory cells define a memory plane within an interconnect portion of the integrated circuit, the memory plane including a plurality of memory cells extending in orthogonal first and second directions;
• word lines traversing the memory plane in the first direction;
• bit lines traversing the memory plane in the second direction;
• first electrically conductive contacts connecting the word lines to the first and second electrode pads;
• and
• a second electrically conductive contact connecting one of the bit lines to the third electrode,
• wherein the first memory cell includes the first electrode pad, the dielectric layer, and the third electrode, and the second memory cell includes the second electrode pad, the dielectric layer, and the third electrode, and
• wherein the dielectric layer extends along the first direction.