Semiconductor device and method of manufacturing the same

A semiconductor device comprising:

• a first fin, a second fin, and a dummy fin on a substrate and extending along a first direction, wherein the dummy fin is disposed between the first and the second fins;
• a first and a second metal gate respectively on the first and the second fins;
• a third and a fourth metal gate respectively on the first and second fins;
• a first isolation structure over the dummy fin and between the first and the second metal gate, wherein the first isolation structure, the first and the second metal gate are aligned in a second direction, which is perpendicular to the first direction;
• a second isolation structure over the dummy fin and between the third and the fourth metal gate, wherein the second isolation structure is next to the first isolation structure, and the second isolation structure, the third and the fourth metal gate are aligned in the second direction;
• a first and a second epitaxial source/drain (S/D) region respectively on the first and the second fin;
• an interlayer dielectric (ILD) layer over the first and the second epitaxial source/drain (S/D) region;
• and
• a metal wire in contact with a top surface of the dummy fin, wherein the metal wire is laterally between the first isolation structure and the second isolation structure along the first direction, and wherein a bottommost surface of the metal wire is higher than a bottommost surface of the first metal gate.

A semiconductor device comprising:

• a first semiconductor fin and a second semiconductor fin on a substrate;
• a dummy fin disposed on the substrate and between the first semiconductor fin and the second semiconductor fin;
• a first metal gate crossing the first semiconductor fin and a second metal gate crossing the second semiconductor fin;
• an isolation structure on and overlapped with the dummy fin, wherein the isolation structure is aligned with the first metal gate and the second metal gate along a lengthwise direction of the first metal gate and the second metal gate, wherein the dummy fin and the isolation structure separates the first metal gate from the second metal gate, and wherein along the lengthwise direction of the first metal gate and the second metal gate, the isolation structure is closer to the second semiconductor fin than to the first semiconductor fin, and the first metal gate extends to a top surface of the dummy fin;
• an interlayer dielectric (ILD) layer adjacent to the isolation structure;
• and
• a metal wire in the ILD layer.