Semiconductor devices with low junction capacitances and methods of fabrication thereof

A semiconductor device comprising:

• a substrate;
• a first dielectric layer;
• a first active area bounded laterally by the first dielectric layer, the first active area having a first thickness;
• a second active area bounded laterally by the first dielectric layer, the first active area being laterally offset from the second active area, the second active area having a second thickness different than the first thickness, the first dielectric layer extending under each of the first active area and the second active area, top surfaces of the first active area and the second active area being at a same level;
• and
• a second dielectric layer below the first dielectric layer, the substrate being interposed between portions of the second dielectric layer.

A semiconductor device comprising:

• a substrate;
• an active area in the substrate, the active area comprising:
• a lower portion with a first width laterally bounded by a first dielectric material,
• an upper portion with a second width laterally bounded by a second dielectric material, the upper portion including a source region, a drain region, and a channel region, the second dielectric material having a lower surface disposed on an upper surface of the first dielectric material, and
• a mid portion interposed between the lower portion and the upper portion, the mid portion having a third width, the third width being a narrowest width laterally bounded by the second dielectric material, the third width being less than the first width and the second width;
• a gate structure formed, at least in part, above the upper portion;
• and
• a dielectric spacer on opposing sides of the upper portion, the dielectric spacer being separated from the active area by the second dielectric material.