US 11,114,560 B2Granted

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

AssigneeFuji Electric Co., Ltd.

InventorKeiji Okumura

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Abstract

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer and a first semiconductor region each of a first conductivity type, and a first base region, a second semiconductor layer and a second semiconductor region each of a second conductivity type. The first base region opposes the second semiconductor region in a depth direction. A distribution of point defects in a depth direction from a first surface of the second semiconductor region, opposite a second surface of the second semiconductor region facing toward a front surface of the silicon carbide semiconductor substrate has two peaks at positions deeper than an interface between the first semiconductor layer and the first base region, where a first peak at a deeper position of the two peaks has a greater quantity of the point defects than does a second peak at a shallower position of the two peaks.

Claims17

Dependent claims

A silicon carbide semiconductor device, comprising:

a silicon carbide semiconductor substrate of a first conductivity type, having a front surface and a back surface opposite to the front surface;
a first semiconductor layer of the first conductivity type, provided on the front surface of the silicon carbide semiconductor substrate, and containing silicon carbide, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate, and further having a first side, and a second side opposite to the first side and facing the front surface of the silicon carbide semiconductor substrate;
a first base region of a second conductivity type, selectively provided in the first semiconductor layer, the first base having a first surface, and a second surface opposite to the first surface and facing the front surface of the silicon carbide semiconductor substrate;
a second semiconductor layer of the second conductivity type, provided on the first side of the first semiconductor layer, and containing silicon carbide;
a first semiconductor region of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer;
a second semiconductor region of the second conductivity type, selectively provided in the surface layer of the second semiconductor layer, and being in contact with the first semiconductor region, the second semiconductor region having a first surface, and a second surface opposite to the first surface and facing the front surface of the silicon carbide semiconductor substrate;
a first electrode in contact with the first semiconductor region and the second semiconductor region;
and
a second electrode provided on the back surface of the silicon carbide semiconductor substrate, wherein
the first base region is provided so as to overlap the second semiconductor region in a depth direction,
in the second semiconductor region, a distribution of point defects in the depth direction from the first surface of the second semiconductor region has first and second peaks at positions deeper than a position of an interface between the first semiconductor layer and the second surface of the first base region, and
the first peak has a deeper position than does the first peak and has a greater quantity of the point defects than does the second peak.

9 more elements

A method of manufacturing a silicon carbide semiconductor device, the method comprising:

forming on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, the first semiconductor layer containing silicon carbide and having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate;
selectively forming a first base region of a second conductivity type in the first semiconductor layer;
forming on a first surface of first semiconductor layer opposite to a second surface thereof facing toward the front surface of the silicon carbide semiconductor substrate, a second semiconductor layer of the second conductivity type and containing silicon carbide;
selectively forming in a surface region of the second semiconductor layer, a first semiconductor region of the first conductivity type;
selectively forming in a surface layer of the second semiconductor layer, a second semiconductor region of the second conductivity type in contact with the first semiconductor region;
forming a first electrode in contact with the first semiconductor region and the second semiconductor region;
and
forming a second electrode on a back surface of the silicon carbide semiconductor substrate, wherein
forming the first base region includes forming the first base region at a position overlapping the second semiconductor region in a depth direction,
forming the first base region and forming the second semiconductor region include forming the first base region and the second semiconductor region so that a distribution of point defects in the depth direction from a first surface of the second semiconductor region, the first surface of the second semiconductor region being opposite to a second surface of the second semiconductor region facing the front surface of the silicon carbide semiconductor substrate, has two peaks at positions deeper than an interface between the first semiconductor layer and the first base region, a first peak of the two peaks being at a position deeper than a shallower second peak of the two peaks, and having a greater quantity of the point defects than does the second peak.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/806,669Filed 2 Mar 2020
Priority: JP JP2019-04946718 Mar 2019
Published: US 2020/0303541 A124 Sep 2020
Granted: 7 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 12/031
Manufacture or treatment: of igbts
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/662
Vertical dmos [vdmos] fets: having a drift region having a doping concentration that is higher between adjacent body regions relative to other…

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US 2020/0303541 A1Pre-grant publication · published 24 Sep 2020
US 11,114,560 B2This patent

From the US filing history. Foreign family members aren’t listed.

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