Gate stack design for GaN e-mode transistor performance

An integrated circuit structure, comprising:

• a dielectric structure;
• a first layer including gallium and nitrogen, the first layer on a top surface and at least one sidewall surface of the dielectric structure;
• a gate stack over the first layer, the gate stack including a barrier structure configured with a charge spillover reducing layer on a lattice grading layer, the charge spillover reducing layer comprising a first group III-N semiconductor compound and the lattice grading layer comprising a second group III-N semiconductor compound that is different from the first group III-N semiconductor compound, wherein the lattice grading layer includes aluminum;
• and
• a first region and a second region each including a group III-V semiconductor material and separated from at least a portion of the gate stack by respective third regions, wherein the first and second regions are n-doped and include nitrogen and one or both of indium and gallium, and wherein the third regions include a group III-V semiconductor material having an aluminum concentration that is greater than the aluminum concentration of the lattice grading layer.

An integrated circuit structure, comprising:

• a first layer including a first group III-V semiconductor material;
• a gate stack over the first layer, and including a second layer between and in contact with third and fourth layers, the second layer comprising a second group III-V semiconductor material, and the third and fourth layers each comprising a third group III-V semiconductor material;
• a source region and a drain region each over the first layer and including a fourth group III-V semiconductor material;
• and
• a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group III-V semiconductor material, wherein the second distance is greater than the first distance.

An integrated circuit structure, comprising:

• a first layer including a first group III-V semiconductor material, wherein the first group III-V semiconductor material consists essentially of gallium and nitrogen;
• a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising a second group III-V semiconductor material, and the third and fourth layers each comprising a third group III-V semiconductor material, wherein the second group III-V semiconductor material consists essentially of aluminum, gallium, and nitrogen, and wherein the third group III-V semiconductor material consists essentially of aluminum and nitrogen;
• a source region and a drain region each over the first layer and including a fourth group III-V semiconductor material, wherein the fourth group III-V semiconductor material comprises gallium, nitrogen, and an n-type dopant;
• and
• a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group III-V semiconductor material, wherein the second distance is greater than the first distance, and wherein the fifth group III-V semiconductor material consists essentially of aluminum, indium, and nitrogen.