US 11,114,546 B2 · Semiconductor device and formation thereof

Abstract

A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.

Claims20

Dependent claims

A semiconductor device, comprising:

a fin over a substrate;
a gate over a top surface of a channel portion of the fin;
a dielectric layer;
and
a contact, wherein:
a first portion of the fin, different than the channel portion of the fin, is in contact with the substrate,
the channel portion of the fin is spaced apart from the substrate,
a first sidewall of the dielectric layer faces the gate,
a second sidewall of the dielectric layer faces the fin,
a first portion of the second sidewall of the dielectric layer is in contact with the fin, and
a second portion of the second sidewall of the dielectric layer is spaced apart from the fin by the contact.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/706,921Filed 9 Dec 2019 · continuation

Priority

31 Mar 2014

Published

US 2020/0111894 A19 Apr 2020

Granted

7 Sep 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes

Family

Application14/230,203Parent of this division · filed 31 Mar 2014

Application15/641,197Parent of this continuation · filed 3 Jul 2017

US 9,698,240 B2Parent of this division · filed 4 Jul 2017

US 2020/0111894 A1Pre-grant publication · published 9 Apr 2020

US 10,505,017 B2Parent of this continuation

Application15/641,197Parent of this division

US 2015/0279964 A1Published application

US 2017/0309725 A1Published application

US 11,114,546 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor device and formation thereof

Life of this patent

Semiconductor device and formation thereof

Life of this patent

Abstract

Claims20