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US 11,114,542 B2Granted
Semiconductor device with reduced gate height budget
AssigneeGlobalFoundries U.S. Inc.
InventorsHui Zang, Haigou Huang
Life of this patent
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Abstract
The present disclosure relates to semiconductor structures and, more particularly, to semiconductor device with reduced gate height budget and methods of manufacture. The method includes: forming a plurality of gate structures on a substrate; recessing material of the plurality of gate structures to below a surface of an insulator material; forming trenches in the insulator material and underlying material adjacent to sidewalls of the plurality of gate structures; and filling the recesses and trenches with a capping material.
Claims19
A structure comprising:
- a plurality of recessed gate structures each of which include gate material and sidewall material formed on sidewalls of the gate material, the plurality of recessed gate structures separated from one another by a cut within the gate material;
- at least one trench structure extending to within an insulator material and a poly material underneath the insulator material, the at least one trench structure being located on sides of the sidewall material which oppose the recessed gate structures;
- and
- a capping material over the plurality of recessed gate structures, between the sidewall material, within the cut and within the at least one trench structure between the poly material and the insulator material on sides of the sidewall material opposing the recessed gate structures.
1 more element
Dependencies are inferred from the claim text.