Semiconductor device including standard cells with header/footer switch including negative capacitance

A semiconductor device, comprising:

• a first potential supply line for supplying a first potential;
• a second potential supply line for supplying a second potential lower than the first potential;
• a functional circuit including a CMOS circuit constituted by normal MOS FETs;
• and
• a switch disposed between the first potential supply line and the CMOS circuit of the functional circuit, wherein:
• a voltage potential of the first potential supply line is supplied to the CMOS circuit via the switch, and
• the switch consists of a negative capacitance (NC) MOS FET,
• in an NC MOS FET, a gate voltage is applied to a gate dielectric layer through a negative capacitor, and in a normal MOS FET, a gate voltage is applied to a gate dielectric layer without a negative capacitor,
• a gate dielectric layer of the NCFET includes a first dielectric layer and a second dielectric layer disposed on and in direct contact with the first dielectric layer, a gate electrode disposed on and in direct contact with the first dielectric layer and the second dielectric layer,
• the second dielectric layer includes a ferroelectric material, and
• a top of the first and second gate dielectric layers is below a top of the gate electrode.

A semiconductor device, comprising:

• a first potential supply line for supplying a first potential;
• a first internal potential supply line and a second internal potential supply line separated from the first internal potential supply line, both for supplying the first potential;
• a second potential supply line for supplying a second potential lower than the first potential;
• a first functional circuit including a PMOS transistor and a NMOS transistor;
• a second functional circuit including a PMOS transistor and a NMOS transistor;
• a first negative capacitance (NC) FET disposed between the first potential supply line and the first internal potential supply line;
• and
• a second NC FET disposed between the first potential supply line and the second internal potential supply line, wherein:
• the NMOS and PMOS transistors are normal MOS FETs,
• in an NC MOS FET, a gate voltage is applied to a gate dielectric layer through a negative capacitor, and in a normal MOS FET, a gate voltage is applied to a gate dielectric layer without a negative capacitor,
• each of the first and second NC FETs includes a first dielectric layer and a second dielectric layer disposed over the first dielectric layer, a gate electrode disposed over the second dielectric layer,
• the second dielectric layer includes a ferroelectric material, and
• a top of the first and second gate dielectric layers is below a top of the gate electrode.