Gate stack for heterostructure device

A heterostructure semiconductor device comprising:

• a first active layer;
• a second active layer disposed on the first active layer, a two-dimensional electron gas layer formed between the first and second active layers;
• a sandwich gate dielectric layer structure disposed on the second active layer, wherein at least one layer of the sandwich gate dielectric layer structure is an ex-situ deposited layer formed through atomic layer deposition (ALD) with O2 plasma as compared to the first active layer and the second active layer and at least another layer of the sandwich gate dielectric layer structure is an in-situ deposited layer formed through metal-organic chemical vapor deposition (MOCVD) as compared to the first active layer and the second active layer, wherein the in-situ deposited layer has a thickness between 30-60 nanometers such that a critical voltage of the heterostructure semiconductor device is between approximately 100-170 volts;
• a passivation layer disposed over the sandwich gate dielectric layer structure;
• a gate that extends through the passivation layer to the top of the sandwich gate dielectric layer structure, wherein the gate is vertically separated from the second active layer by the sandwich gate dielectric layer structure and the sandwich gate dielectric layer structure is beneath a bottommost surface of the gate;
• and
• first and second ohmic contacts disposed on the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts, wherein the two-dimensional electron gas layer is formed between the first and second active layers beneath the first and second ohmic contacts and the gate, wherein the heterostructure semiconductor device is a high-voltage FET.