Transistor with an airgap spacer adjacent to a transistor gate

A microelectronic transistor, comprising:

• a microelectronic substrate;
• a source region and a drain region formed in the microelectronic substrate;
• a single layer of interlayer dielectric disposed over the microelectronic substrate;
• a source contact extending through the interlayer dielectric and electrically contacting the source region;
• a drain contact extending through the interlayer dielectric and electrically contacting the drain region;
• a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode;
• a gate hard mask, wherein the gate extends through the gate hard mask;
• and
• an airgap spacer positioned between the gate and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the gate, an exposed portion of the gate hard mask, and an exposed portion of the single layer of interlayer dielectric, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

An electronic system, comprising:

• a board;
• and
• a microelectronic component attached to the board, wherein the microelectronic component includes a microelectronic transistor comprising:
• a microelectronic substrate;
• a source region and a drain region formed in the microelectronic substrate;
• a single layer of interlayer dielectric disposed over the microelectronic substrate;
• a source contact extending through the interlayer dielectric and electrically contacting the source region;
• a drain contact extending through the interlayer dielectric and electrically contacting the drain region;
• a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode;
• and
• an airgap spacer positioned between the gate and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the single layer of interlayer dielectric, and an exposed portion of the gate, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

An electronic system, comprising:

• a board;
• and
• a microelectronic component attached to the board, wherein the microelectronic component includes a microelectronic transistor comprising:
• a microelectronic substrate;
• a source region and a drain region formed in the microelectronic substrate;
• a signal layer of interlayer dielectric disposed over the microelectronic substrate;
• a source contact extending through the interlayer dielectric and electrically contacting the source region;
• a drain contact extending through the interlayer dielectric and electrically contacting the source region;
• a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode;
• and
• a gate hard mask, wherein the gate extends through the gate hard mask;
• and
• an airgap spacer positioned between the gate electrode and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the gate, an exposed portion of the gate hard mask, and an exposed portion of the single layer of interlayer dielectric, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.