Enhancement-mode high electron mobility transistor

A method for manufacturing an enhancement-mode high electron mobility transistor, wherein the method comprises:

• providing a stack of layers comprising:
• a substrate;
• a III-V channel layer over the substrate;
• a III-V barrier layer on the III-V channel layer;
• a p-doped III-V layer on the III-V barrier layer, wherein the p-doped III-V layer has a first surface area;
• and
• a Schottky contact interlayer on the p-doped III-V layer, wherein the Schottky contact interlayer has a surface that is in contact with the p-doped III-V layer and that has a second surface area, wherein the second surface area is less than the first surface area, and wherein the second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered by the Schottky contact interlayer;
• and
• depositing a metal gate on the Schottky contact interlayer, thereby forming an interface between the metal gate and the Schottky contact interlayer such that entire interface has a third surface area, wherein the third surface area is less than the second surface area.