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US 11,114,536 B1Granted
Semiconductor device having multiple dimensions of gate structures and method for fabricating the same
AssigneeNanya Technology Corporation
InventorCheng-Ling Yang
Life of this patent
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Abstract
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area adjacent to the array area, a first gate structure positioned in the array area, and a second gate structure positioned in the peripheral area. A width of the first gate structure is less than a width of the second gate structure, and a depth of the first gate structure is less than a depth of the second gate structure.
Claims19
A semiconductor device, comprising:
- a substrate comprising an array area and a peripheral area adjacent to the array area;
- a first gate structure positioned in the array area;
- and
- a second gate structure positioned in the peripheral area;
- wherein a width of the first gate structure is less than a width of the second gate structure, and a depth of the first gate structure is less than a depth of the second gate structure;
- wherein the first gate structure comprises a first gate insulating layer inwardly positioned in the array area, a first gate conductive layer positioned on the first gate insulating layer, and a first bottom capping layer positioned on the first gate conductive layer, wherein a top surface of the first bottom capping layer is at a same vertical level as a top surface of the substrate.
3 more elements
A method for fabricating a semiconductor device, comprising:
- providing a substrate comprising an array area and a peripheral area adjacent to the array area;
- forming a first gate structure in the array area;
- and
- forming a second gate structure in the peripheral area and having a width greater than a width of the first gate structure and a depth greater than a depth of the first gate structure;
- wherein the first gate structure comprises a first gate insulating layer inwardly positioned in the array area, a first gate conductive layer positioned on the first gate insulating layer, and a first bottom capping layer positioned on the first gate conductive layer, wherein a top surface of the first bottom capping layer is at a same vertical level as a top surface of the substrate.
2 more elements
Dependencies are inferred from the claim text.