US 11,114,534 B2 · Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same

Abstract

A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

Claims20

Dependent claims

A three-dimensional memory device, comprising:

an alternating stack of source layers and drain layers located over a substrate;
memory openings vertically extending through the alternating stack;
vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack;
vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers;
and
vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines, wherein each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

3 more elements

A method of forming a three-dimensional memory device, comprising:

forming a vertical repetition of a unit layer stack that comprises a doped semiconductor source layer, a channel-level spacer layer, a doped semiconductor drain layer, and an inter-transistor-level insulating layer over a substrate;
forming memory openings vertically extending through the vertical repetition;
forming a vertical stack of channel cavities around each of the memory openings by laterally recessing the channel-level spacer layers relative to the doped semiconductor source layers, the doped semiconductor drain layers, and the inter-transistor-level insulating layers;
forming semiconductor oxide spacers by oxidizing surface portions of at least the doped semiconductor source layers and the doped semiconductor drain layers;
forming a semiconductor channel and a memory material portion within each of the channel cavities;
and
forming a vertical word line in each of the memory openings.

4 more elements

Dependencies are inferred from the claim text.

Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same

Life of this patent

Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same

Life of this patent

Abstract

Claims20