Power transistor with dV/dt controllability and tapered mesas
AssigneeInfineon Technologies Austria AG
InventorsMatteo Dainese, Markus Beninger-Bina, Alexander Philippou
Life of this patent
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Abstract
A power transistor having a semiconductor barrier region is presented. A power unit cell of the power transistor has at least two trenches that may both extend into the semiconductor barrier region. The semiconductor barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The semiconductor barrier region can be electrically floating. Further, the at least two trenches may both increase in width along their respective extension into the semiconductor body.
Claims21
A power semiconductor transistor, comprising:
- a semiconductor body coupled to a first load terminal and a second load terminal of the transistor and comprising a drift region of a first conductivity type configured to conduct a load current between the first and second load terminals;
- at least one power unit cell comprising:
- at least one control trench having a control trench electrode;
- at least one further trench having a further trench electrode;
- at least one active mesa comprising a source region of the first conductivity type and electrically connected to the first load terminal and a channel region of a second conductivity type and separating the source region and the drift region, wherein, in the at least one active mesa, at least a respective section of each of the source region, the channel region and the drift region are arranged adjacent to a sidewall of the at least one control trench, and wherein the control trench electrode is configured to receive a control signal from a control terminal of the power semiconductor transistor and to control the load current in the at least one active mesa;
- a semiconductor barrier region of the second conductivity type formed in the semiconductor body and overlapping with at least 50% of a first width of the at least one active mesa and with a bottom of the at least one further trench,
- wherein the at least one active mesa has the first width at the channel region and a second width at an opening portion of the at least one active mesa, the second width being smaller than 75% of the first width,
- wherein a p-n junction between the channel region and the drift region is disposed in an upper region of the at least one active mesa which has the first width,
- wherein the semiconductor barrier region comprises one or more openings, wherein one or more sections of the drift region extend through the one or more openings, and wherein the one or more openings laterally overlap with the at least one active mesa.
A power semiconductor transistor comprising at least one power unit cell having an insulated gate transistor configuration and a control trench and a source trench, the control trench and the source trench laterally confining an active mesa, wherein each of the control trench, the source trench and the active mesa extends into an electrically floating semiconductor barrier region of a second conductivity type, and wherein a width of the active mesa decreases by at least 25% along a total vertical extension of the active mesa, wherein the active mesa comprises a source region of a first conductivity type, a channel region of the second conductivity type disposed below the source region, and a drift region of the first conductivity type disposed below the channel region, and wherein the width of the active mesa decreases only at locations below an upper portion of the at least one active mesa that comprises a p-n junction between the channel region and the drift region, wherein the semiconductor barrier region comprises one or more openings, wherein one or more sections of the drift region extend through the one or more openings, and wherein the one or more openings laterally overlap with the at least one active mesa.
Dependencies are inferred from the claim text.