Semiconductor device and method for manufacturing same

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a semiconductor layer formed on the semiconductor substrate and including an active region, the active region including:
• a back-gate region;
• a source region surrounding the back-gate region in a plan view;
• and
• a drain region surrounding the source region in the plan view,
• a first device isolation portion formed in the semiconductor layer, the first device isolation portion surrounding the active region of the semiconductor layer in the plan view;
• a first terrace insulating film formed between the source region and the drain region, the first terrace insulating film formed on the semiconductor layer;
• a gate insulating film formed on the semiconductor layer;
• a gate electrode formed on the gate insulating film, the gate electrode being partially formed on the first terrace insulating film;
• an interlayer insulating film formed on the semiconductor layer so as to cover the gate electrode;
• a first plug formed in the interlayer insulating film and formed on a first portion of the source region;
• a second plug formed in the interlayer insulating film and formed on a second portion of the source region;
• a first buried layer of a second conductivity type different from a first conductivity type of the semiconductor substrate, the first buried layer being formed in the semiconductor layer;
• a second buried layer of the first conductivity type formed on the first buried layer;
• and
• a junction isolating part of the first conductivity type surrounding the first device isolation portion in the plan view, the junction isolating part reaching the second buried layer,
• wherein a thickness of the first terrace insulating film is smaller than a thickness of the first device isolation portion,
• wherein a cell pitch which is a distance between a center part of the source region and a center part of the drain region is shorter than 5 μm in a channel length direction,
• wherein, in the plan view, the back-gate region, the source region, the drain region, the first device isolation portion, the gate electrode and the junction isolating part overlap with the first buried layer, and
• wherein, in the plan view, the back-gate region, the source region, the drain region, the first device isolation portion, and the gate electrode overlap with the second buried region.