Thin film transistor and manufacture method thereof, array substrate and manufacture method thereof

A manufacture method of a thin film transistor, comprising:

• providing a base substrate;
• and
• forming a gate electrode, a first electrode, a second electrode, and a semiconductor layer of the thin film transistor on the base substrate, wherein at least one of a group consisting of the gate electrode, the first electrode, and the second electrode comprises N portions that are stacked in a direction perpendicular to the base substrate, adjacent two portions of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2,
• wherein the method comprises:
• performing N patterning processes to respectively form the N portions,
• wherein the semiconductor layer comprises an upper surface away from the base substrate, a first side surface and a second side surface that intersect the upper surface, and the first side surface is opposite to the second side surface, and
• the first electrode is in direct contact with the upper surface and the first side surface, and the second electrode is in direct contact with the upper surface and the second side surface.

A thin film transistor, comprising:

• a gate electrode, a first electrode, a second electrode, and a semiconductor layer, wherein the gate electrode comprises N1 portions that are stacked in a direction perpendicular to a base substrate, the first electrode comprises N2 portions that are stacked in the direction perpendicular to the base substrate, and the second electrode comprises N3 portions that are stacked in the direction perpendicular to the base substrate;
• N1, N2, and N3 are all positive integers more than or equal to 2;
• adjacent two portions of the N1 portions are in direct contact with each other, adjacent two portions of the N2 portions are in direct contact with each other, and adjacent two portions of the N3 portions are in direct contact with each other;
• in a direction from a position close to the base substrate to a position away from the base substrate, the N1 portions are sequentially a first portion, a second portion . . . , and a N1-th portion, the N2 portions are sequentially a first portion, a second portion . . . , and a N2-th portion, and the N3 portions are sequentially a first portion, a second portion . . . , and a N3-th portion;
• and
• a M1-th portion of the gate electrode, a M2-th portion of the first electrode, and a M3-th portion of the second electrode are in a same layer, wherein M1 is a positive integer less than or equal to N1, M2 is a positive integer less than or equal to N2, and M3 is a positive integer less than or equal to N3.