Thin film transistors having relatively increased width and shared bitlines

An integrated circuit structure, comprising:

• an array of transistors formed in an insulator structure above a substrate, wherein each of the transistors comprises a lateral arrangement of:
• a gate in the insulating structure, a source laterally adjacent to a first side of the gate, and a drain laterally adjacent to an opposite a second side of the gate, the array of transistors arranged in rows of laterally adjacent transistors, and columns such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor in a same column, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width;
• and
• first conductive contacts that connect the drains along respective columns of the array such that each of the single conductive contacts are shared between neighboring pairs of transistors in each row of the array, and wherein the first conductive contact extends through the insulator structure at least two interconnect levels.

A method of fabricating an array of thin film transistors, the method comprising:

• forming an insulating structure over a substrate to a desired interconnect level over conductive lines representing source and drain lines on a substrate;
• forming vias and backbone trenches in the insulating structure;
• filling the vias and backbone trenches with conductive metal to form conductive contacts representing source lines and drain lines, wherein the conductive contacts formed in the backbone trenches span columns of the array to form shared bitlines;
• forming a photoresist mask on top of the insulating structure with openings defining locations of channel areas between the source and drain lines;
• forming channel area trenches by etching the insulating structure in the locations defining the channel areas to a same interconnect level as the insulating;
• forming a semiconducting oxide material in the channel trench areas;
• forming a gate dielectric layer over the semiconducting oxide material in the channel area trenches;
• forming a gate electrode on the gate dielectric layer to fill-in the channel trench areas forming vias on the gate electrode;
• and
• forming wordlines on an uppermost surface of the vias, wherein the wordlines are laid out perpendicular to the shared bitlines.