Semiconductor device

A semiconductor device, comprising:

• gate electrodes stacked in a direction perpendicular to an upper surface of a substrate, each of the gate electrodes including:
• subgate electrodes spaced apart from each other, and
• gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other;
• isolation regions extending in a first direction and passing through the gate electrodes, the isolation regions being spaced apart from each other in the first direction, and the gate connection portions being between adjacent ones of the isolation regions;
• channels extending through the gate electrodes perpendicularly to the upper surface of the substrate;
• dummy channels extending perpendicularly to the upper surface of the substrate, the dummy channels arranged on at least one side of at least a portion of the gate connections portions in a second direction;
• a wiring insulation layer on the channels and the dummy channels;
• wiring lines on the wiring insulation layer, the wiring lines overlapping the channels and at least some of the dummy channels along a vertical direction;
• and
• channel plugs passing through the wiring insulation layer and connecting the channels and at least some of the wiring lines,
• wherein upper surfaces of the dummy channels are entirely covered with the wiring insulation layer, such that the dummy channels are not electrically connected to the wiring lines.

A semiconductor device, comprising:

• a substrate having a first region and a second region;
• gate electrodes stacked perpendicularly to an upper surface of the substrate in the first region, and extending to different lengths in a first direction in the second region;
• first isolation regions extended in the first direction while passing through the gate electrodes in the first region and the second region, the first isolation regions being spaced apart from each other in a second direction perpendicular to the first direction;
• second isolation regions passing through the gate electrodes between the first isolation regions, the second isolation regions being spaced apart from each other in the first direction;
• channels extending perpendicularly to the upper surface of the substrate through the gate electrodes in the first region;
• dummy channels extending perpendicularly to the upper surface of the substrate through the gate electrodes in the second region, the dummy channels including first dummy channels arranged in rows and columns and second dummy channels on both sides of a separation region in the second direction, the separation region being a region in which adjacent ones of the second isolation regions are spaced apart from each other in the first direction;
• upper isolation regions extending in the first direction, and passing through at least one gate electrode including a gate electrode in an uppermost portion among the gate electrodes, between the second isolation regions and the first isolation regions;
• and
• a lower isolation region passing only through some of the gate electrodes, the lower isolation region passing at least through one gate electrode including a gate electrode in a lowermost portion among the gate electrodes, in a region vertically overlapping the separation region.