One-time programable memory device having enhanced program efficiency and method for fabricating the same

A one-time programmable (OTP) memory device comprising:

• a plurality of active regions extending in a first direction and disposed in a well region to be spaced apart from each other in a second direction intersecting the first direction;
• a plurality of selection gate electrodes extending in the second direction to cross the plurality of active regions and being spaced apart from each other in the first direction;
• and
• a plurality of floating gates arrayed in a matrix form to cross the plurality of active regions and to include plural groups of floating gates,
• wherein if “i’ is an odd number, an ith selection gate electrode and an (i+1)th selection gate electrode among the plurality of selection gate electrodes are disposed to be adjacent to each other between an ith group of floating gates arrayed in the second direction among the plural groups of floating gates and an (i+1)th group of floating gates arrayed in the second direction among the plural groups of floating gates,
• wherein drain regions are respectively disposed in the active regions between the ith selection gate electrode and the (i+1)th selection gate electrode,
• wherein common junction regions are respectively disposed in the active regions between each of the plurality of selection gate electrodes and the floating gates adjacent thereto;
• wherein source regions are respectively disposed in the active regions between the ith group of floating gates and an (i−1)th group of floating gates among the plural groups of floating gates,
• wherein a length of an overlapping region between the source region and the floating gate in the first direction is less than a length of an overlapping region between the common junction region and the floating gate in the first direction, and
• wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.

A one-time programmable (OTP) memory device including a plurality of unit cells, each of the plurality of unit cells comprising:

• a selection transistor including a drain region separated from a common junction region by a first channel region;
• and
• a storage transistor including a source region separated from the common junction region by a second channel region and a floating gate structure disposed over the second channel region,
• wherein a length of an overlapping region between the source region and the floating gate structure of the storage transistor is smaller than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction of the storage transistor, and
• wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.

A one-time programmable (OTP) memory device including a plurality of unit cells which are respectively located at cross points of word lines respectively disposed in a plurality of rows and bit lines respectively disposed in a plurality of columns, wherein each of the plurality of unit cells comprises:

• a selection transistor including a drain region separated from a common junction region by a first channel region;
• and
• a storage transistor including a source region separated from the common junction region by a second channel region and a floating gate structure disposed over the second channel region,
• wherein the drain region, the common junction region, and the source region are disposed in a well region,
• wherein the drain region is coupled to any one of the bit lines,
• wherein the source region is coupled to a common source line,
• wherein a length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction of the storage transistor,
• wherein the OTP memory device is programmed by applying a ground voltage to the common source line and by applying a positive program voltage to the one of the bit lines and the well region, and
• wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.