Computation-in-memory in three-dimensional memory device

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising a peripheral circuit, a data processing circuit, and a first bonding layer comprising a plurality of first bonding contacts;
• a second semiconductor structure comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts;
• and
• a bonding interface between the first bonding layer and the second bonding layer, wherein
• the first bonding contacts are in contact with the second bonding contacts at the bonding interface,
• the first semiconductor structure is above the second semiconductor structure, and
• the first semiconductor structure further comprises a semiconductor layer above the first bonding layer, and a pad-out interconnect layer above the semiconductor layer.