Integrated circuit device

An integrated circuit device comprising:

• a memory comprising
• a memory stack comprising
• a plurality of bit lines extending in a first horizontal direction,
• a memory cell interconnection comprising a plurality of upper conductive patterns configured to be electrically connectable to the plurality of bit lines, and
• a memory cell insulation surrounding the memory stack and the memory cell interconnection;
• a peripheral circuit comprising
• a peripheral circuit board,
• a peripheral circuit region on the peripheral circuit board, and
• a peripheral circuit interconnection comprising a plurality of lower conductive patterns between the peripheral circuit region and the memory and bonded to the memory cell interconnection;
• a conductive bonding on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, the conductive bonding being bonded first upper conductive pattern selected from among the plurality of upper conductive patterns and a first lower conductive pattern selected from among the plurality of lower conductive patterns;
• and
• a plurality of through electrodes extended in the vertical direction through one of the memory cell insulation and the peripheral circuit board, in a second region spaced apart from the first region in a horizontal direction,
• wherein the plurality of through electrodes comprise a plurality of first through electrodes arranged in a line along the first horizontal direction in the second region.

An integrated circuit device comprising:

• a memory comprising
• a semiconductor layer,
• a memory stack on the semiconductor layer,
• a memory cell interconnection comprising a plurality of upper conductive patterns overlapping the memory stack in a vertical direction and configured to be electrically connectable to the memory stack, and
• a memory cell insulation surrounding the semiconductor layer, the memory stack, and the memory cell interconnection;
• a peripheral circuit comprising
• a peripheral circuit board,
• a peripheral circuit region on the peripheral circuit board, and
• a peripheral circuit interconnection between the peripheral circuit region and the memory and bonded to the memory cell interconnection;
• a plurality of conductive bonding structures comprising Cu and on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in the vertical direction;
• a plurality of lower conductive patterns comprising at least one metal selected from among Al, W, and Cu and in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction;
• and
• a through electrode penetrating one of the memory cell insulation and the peripheral circuit board in the second region and contacting one lower conductive pattern among the plurality of lower conductive patterns.