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US 11,114,416 B2Granted
Power and temperature management for functional blocks implemented by a 3D stacked integrated circuit
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
Estimating the term…
Abstract
A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, a logic die, and a thermal management component. The non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked. The thermal management component can be stacked in between the non-volatile memory die and the logic die, stacked in between the volatile memory die and the logic die, or both.
Claims20
An apparatus comprising:
- a non-volatile memory die;
- a volatile memory die;
- a logic die;
- and
- a thermal management component having a different thermal conductivity than the dies,
- wherein the non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked,
- wherein the non-volatile memory die, the volatile memory die, and the logic die are arranged to form an array of functional blocks.
4 more elements
An apparatus, comprising:
- a logic die;
- a 3D XPoint (3DXP) die;
- a dynamic random-access memory (DRAM) die, wherein the logic die is stacked between the 3DXP die and the DRAM die;
- a plurality of through silicon vias (TSVs) that interconnect the logic die, the 3DXP die, and the DRAM die and that run through the dies;
- and
- a thermal management component, wherein the thermal management component has a different thermal conductivity than the dies, wherein the 3DXP die, the DRAM die, and the logic die are arranged to form an array of functional blocks.
3 more elements
An apparatus, comprising:
- a 3D XPoint (3DXP) die comprising an array of non-volatile memory partitions, wherein each partition of the array of non-volatile memory partitions comprises an array of non-volatile memory cells;
- a volatile memory die comprising an array of volatile memory partitions, wherein each partition of the array of volatile memory partitions comprises an array of volatile memory cells;
- a logic die comprising an array of logic partitions, wherein the 3DXP die, the volatile memory die, and the logic die are stacked;
- a through silicon via (TSV) that connects and runs through a respective non-volatile memory partition, a respective logic partition, and a respective volatile partition in a respective column of the 3D SIC;
- and
- a thermal management component, wherein the thermal management component has a different thermal conductivity than the dies.
3 more elements
Dependencies are inferred from the claim text.