Wafer structure with capacitive chip interconnection, method for manufacturing the same, and chip structure with capacitive chip interconnection

A wafer structure, comprising a wafer bonding structure, wherein the wafer bonding structure comprises a first wafer and a second wafer that are stacked with each other with a front surface of the first wafer facing toward a front surface of the second wafer, and the wafer bonding structure further comprises a plurality of chip structures arranged in an array, wherein

• each of the chip structures comprises:
• a first chip, wherein the first chip comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer;
• and
• a second chip, wherein the second chip comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer;
• wherein the first chip is stacked with the second chip via the first bonding layer and the second bonding layer with a front surface of the first chip facing toward a front surface of the second chip, and the first capacitor plate is arranged facing toward the second capacitor plate with at least the second dielectric material and the fourth dielectric material being provided between the first capacitor plate and the second capacitor plate;
• wherein the first plate interconnection structure comprises an interconnection layer connected to the first capacitor plate;
• and
• wherein the first bonding layer is arranged with a bonding pad to lead out the interconnection layer of the first device interconnection structure, and the second bonding layer is arranged with a bonding pad to lead out an interconnection layer of the second device interconnection structure, and wherein the bonding pad of the first bonding layer is aligned with the bonding pad of the second bonding pad.

A method for manufacturing a wafer structure, comprising:

• providing a first wafer, wherein the first wafer is provided with first chips arranged in an array, and each of the first chips comprises a first substrate, a first cover layer of a first dielectric material on a front surface of the first substrate, a first capacitor plate and a first plate interconnection structure electrically connected to the first capacitor plate that are arranged in the first cover layer, and a first bonding layer of a second dielectric material on the first cover layer;
• providing a second wafer, wherein the second wafer is provided with second chips arranged in an array, and each of the second chips comprises a second substrate, a second cover layer of a third dielectric material on a front surface of the second substrate, a second capacitor plate and a second plate interconnection structure electrically connected to the second capacitor plate that are arranged in the second cover layer, and a second bonding layer of a fourth dielectric material on the second cover layer;
• and
• bonding the first wafer and the second wafer together via the first bonding layer and the second bonding layer, to obtain a wafer bonding structure in which the first wafer is stacked with the second wafer with a front surface of the first wafer facing toward a front surface of the second wafer, wherein the first capacitor plate is arranged facing toward the second capacitor plate with at least the second dielectric material and the fourth dielectric material being provided between the first capacitor plate and the second capacitor plate;
• wherein the first plate interconnection structure comprises an interconnection layer connected to the first capacitor plate;
• and
• wherein the first bonding layer is arranged with a bonding pad to lead out the interconnection layer of the first device interconnection structure, and the second bonding layer is arranged with a bonding pad to lead out an interconnection layer of the second device interconnection structure, and wherein the bonding pad of the first bonding layer is aligned with the bonding pad of the second bonding pad.