Bonding structure and method for manufacturing the same
AssigneeWuhan Xinxin Semiconductor Manufacturing Co., Ltd.
InventorsFei Liang, Jing Cao, Sheng Hu
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Abstract
A bonding structure and a method for manufacturing the bonding structure are provided. Multiple chips arranged in an array are formed on a surface of a wafer. Each of the chips includes a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure. The first package pad layer is arranged at an edge region of the chip. A chip stack is obtained after bonding and cutting the multiple wafers, and the first package pad layer at the edge region of the chip is exposed.
Claims12
A method for manufacturing a bonding structure, comprising:
- providing a plurality of wafers, wherein each of the plurality of wafers has a first surface and a second surface opposite to the first surface;
- a plurality of chips arranged in an array is formed on the first surface, and each of the plurality of chips comprises a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure;
- and the first package pad layer is arranged at an edge region of the chip;
- bonding the plurality of wafers via bonding layers, to form a wafer stack;
- cutting the wafer stack along a scribe line located among the plurality of chips to obtain a chip stack;
- exposing the first package pad layer at the edge region of each chip in the chip stack;
- providing a package substrate, wherein the package substrate is provided with electrical connections and a second package pad layer electrically connected to the electrical connections;
- and
- electrically connecting the first package pad layer of each chip in the chip stack to the second package pad layer of the package substrate.
A bonding structure, comprising:
- a chip stack formed by laminating chips in sequence, wherein a bonding layer is arranged between every two adjacent ones of the chips, and each chip comprises:
- a device structure,
- an interconnect structure electrically connected to the device structure, and
- a first package pad layer electrically connected to the interconnect structure,
- wherein the first package pad layer is arranged at an edge region of said chip;
- and a package substrate, provided with electrical connections and a second package pad layer electrically connected to the electrical connections,
- wherein the first package pad layer of each chip in the chip stack is electrically connected to the second package pad layer of the package substrate.
Dependencies are inferred from the claim text.