3D stacked memory and vertical interconnect structures for 3D stacked memory

A 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate,

• wherein vertical memory stacks, a trench and a vertical interconnect structure are provided in the cell region,
• wherein the vertical interconnect structure includes:
• a via-hole formed along a vertical direction of the cell region;
• and
• a conductive pillar shaped by filling the via-hole with a conductive material,
• wherein the cell region includes:
• a stacked structure formed by alternately stacking an electrode layer and a
• control gate with a surface thereof surrounded by a first gate insulating film stack on the substrate and arranged on a side surface of the vertical interconnect structure;
• and
• a plurality of cell plugs formed to penetrate through the stacked structure in the vertical direction,
• wherein each of the cell plugs includes a main gate formed in a pillar shape along the vertical direction of the substrate, a second gate insulating film stack along an outer peripheral surface of the main gate, and a channel region formed along an outer peripheral surface of the second gate insulating film stack,
• wherein the via-hole of the vertical interconnect structure is formed to penetrate through the stacked structure configured on the substrate,
• wherein the trench is arranged between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide material and
• wherein a lower end of the vertical interconnect structure is electrically connected to a conductive wiring line, a conductive region provided on the substrate, or a specific wiring line region of a circuit portion.

A 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate,

• wherein vertical memory stacks, a trench and a vertical interconnect structure are provided in the cell region,
• wherein the vertical interconnect structure includes:
• a via-hole formed along a vertical direction of the cell region;
• and
• a conductive pillar shaped by filling the via-hole with a conductive material,
• wherein the cell region includes:
• a stacked structure formed by alternately stacking an electrode layer and a control gate with a surface thereof surrounded by the gate insulating film stack on the substrate;
• and
• a plurality of cell plugs formed to penetrate through the stacked structure in the vertical direction,
• wherein each of the cell plugs includes a word line formed in a pillar shape along the vertical direction of the substrate, a gate insulating film stack formed on an outer peripheral surface of the word line, and a semiconductor layer for forming a channel in a pipe shape formed between the electrode layers along an outer peripheral surface of the gate insulating film stack,
• wherein the trench is arranged between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide, and
• wherein a lower end of the vertical interconnect structure is electrically connected to a conductive wiring line, a conductive region provided on the substrate, or a specific wiring line region of a circuit portion.