Semiconductor structure with buried conductive line and method for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
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Abstract
A semiconductor structure is provided. The semiconductor structure includes a first well region over a substrate, and an isolation structure over the first well region. The semiconductor structure also includes a first transistor over the first well region, and a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor. A top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure.
Claims20
A semiconductor structure, comprising:
- a first well region over a substrate;
- an isolation structure over the first well region;
- a first transistor over the first well region, wherein the first transistor comprises a gate structure and a gate spacer over sidewalls of the gate structure;
- and
- a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor, wherein a top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure, and wherein a portion of the first buried conductive line is covered by the gate spacer.
A semiconductor structure, comprising:
- an N-type well region and a P-type well region over a substrate, wherein the P-type well region adjoins the N-type well region;
- an isolation structure over the N-type well region and the P-type well region;
- a PMOS transistor and a first buried conductive line over the N-type well region, wherein a portion of the isolation structure is sandwiched between the first buried conductive line and the N-type well region;
- a first contact over a source structure of the PMOS transistor, wherein a portion of the first buried conductive line overlaps the first contact;
- and
- an NMOS transistor and a second buried conductive line over the P-type well region, wherein the PMOS transistor and the NMOS transistor share a gate structure.
A method for forming a semiconductor structure, comprising:
- forming a first well region in a substrate;
- forming a first fin structure over the first well region;
- forming an isolation structure over the first well region, wherein the first fin structure protrudes from the isolation structure;
- partially removing the isolation structure to form a first trench over the first well region, wherein the first trench and the first fin structure are parallel to each other, and the first well region is exposed by the first trench;
- forming a first buried conductive line in the first trench, wherein the first buried conductive line extends into a top portion of the first well region;
- and
- forming a first transistor over the first well region after the first buried conductive line is formed, wherein the first buried conductive line is electrically connected to a source structure of the first transistor.
Dependencies are inferred from the claim text.