Self-protective layer formed on high-k dielectric layers with different materials

A method of forming a semiconductor device, the method comprising:

• removing, in a p-type device region, a first dummy gate surrounded by a dielectric layer to form a first opening in the dielectric layer, wherein the first opening exposes a first channel region of a first fin and a first channel region of a second fin;
• removing, in an n-type device region, a second dummy gate and a third dummy gate surrounded by the dielectric layer to form a second opening and a third opening in the dielectric layer, the third opening being between the first opening and the second opening, wherein the second opening exposes a second channel region of the first fin and a second channel region of the second fin, and the third opening exposes a third channel region of the first fin and a third channel region of the second fin;
• forming a first gate dielectric layer extending along sidewalls and a bottom of the first opening, the first gate dielectric layer being a first single-layer dielectric material;
• forming a second gate dielectric layer extending along sidewalls and bottoms of the second and the third openings, the second gate dielectric layer being a second single-layer dielectric material different from the first single-layer dielectric material;
• forming a first work function tuning layer over and contacting the first gate dielectric layer in the first opening and the second gate dielectric layer in the second and third openings;
• forming a first mask layer over the first work function tuning layer, wherein the first mask layer exposes the first opening, where a first portion of the first mask layer fills the second opening, wherein a second portion of the first mask layer covers the first work function tuning layer around the third channel region of the second fin and exposes the first work function tuning layer around the third channel region of the first fin;
• after forming the first mask layer, etching the first work function tuning layer using an etching solution that chemically reacts with the first gate dielectric layer and the second gate dielectric layer, wherein etching the first work function tuning layer removes the first work function tuning layer disposed around the first fin and the second fin in the first opening, and removes the first work function tuning layer disposed around the first fin in the third opening, wherein the first work function tuning layer disposed around the second fin in the third opening remains after the etching, wherein a first self-protective layer is formed in the first opening over the first gate dielectric layer around the first fin and the second fin by a chemical reaction between the etching solution and the first gate dielectric layer, wherein a second self-protective layer is formed in the third opening over the second gate dielectric layer around the third channel region of the first fin by a chemical reaction between the etching solution and the second gate dielectric layer, wherein the first mask layer shields the first work function tuning layer around the third channel region of the second fin from the etching solution;
• removing the first mask layer after the etching;
• after removing the first mask layer, forming a second work function tuning layer, wherein in the first opening, the second work function tuning layer is formed over the first self-protective layer around the first fin and around the second fin, wherein the second opening is free of the second work function tuning layer, wherein in the third opening, the second work function tuning layer is formed over the second self-protective layer around the first fin but not around the second fin;
• and
• filling the first opening, the second opening and the third opening using a conductive material to form a first gate electrode, a second gate electrode, and a third gate electrode, respectively.

A method for forming a semiconductor device, the method comprising:

• forming, in a p-type device region, a first gate dielectric layer around a first channel region of a first fin and around a first channel region of a second fin, the first channel region of the first fin and the first channel region of the second fin being exposed by a first opening in a dielectric layer, the first gate dielectric layer being a first single-layer dielectric material;
• forming, in an n-type device region, a second gate dielectric layer around a second channel region of the first fin, around a second channel region of the second fin, around a third channel region of the first fin, and around a third channel region of the second fin, wherein the second channel region of the first fin and the second channel region of the second fin are exposed by a second opening in the dielectric layer, wherein the third channel region of the first fin and the third channel region of the second fin are exposed by a third opening in the dielectric layer, wherein the third opening is between the first opening and the second opening, wherein the second gate dielectric layer is a second single-layer dielectric material different from the first single-layer dielectric material, wherein the first gate dielectric layer and the second gate dielectric layer extend along and contact an upper surface of the dielectric layer, wherein a first sidewall of the first gate dielectric layer contacts and extends along a second sidewall of the second gate dielectric layer;
• forming a first work function tuning layer on the first gate dielectric layer in the first opening and on the second gate dielectric layer in the second and third openings;
• removing the first work function tuning layer from the first channel region of the first fin and from the third channel region of the first fin using an etching solution, wherein the first work function tuning layer around the second channel region of the first fin and around the third channel region of the second fin are protected from the etching solution, wherein the etching solution includes phosphoric acid and boric acid, wherein after removing the first work function tuning layer, a first self-protective layer and a second self-protective layer are formed on the first gate dielectric layer and the second gate dielectric layer, respectively, by chemical reactions between the etching solution and the first gate dielectric layer and the second gate dielectric layer, wherein the first self-protective layer and the second self-protective layer have different compositions, wherein the first self-protective layer extends around the first channel region of the first fin and the first channel region of the second fin, and the second self-protective layer extends around the third channel region of the first fin, wherein the third channel region of the second fin is free of the first self-protective layer and the second self-protective layer;
• after removing the first work function tuning layer, forming a second work function tuning layer around the first channel region of the first fin, around the first channel region of the second fin, and around the third channel region of the first fin, wherein the third channel region of the second fin, the second channel region of the first fin, and the second channel region of the second fin are free of the second work function tuning layer;
• and
• filling the first opening, the second opening, and the third opening with a conductive material to form a first gate electrode, a second gate electrode, and a third gate electrode, respectively.