High density logic formation using multi-dimensional laser annealing

A method of forming transistor devices, the method comprising:

• forming a first transistor plane as a transistor-based circuit device on a substrate, the first circuit device including channels of field effect transistors;
• depositing a first insulator layer on the first transistor plane;
• depositing a first layer of polycrystalline silicon on the first insulator layer;
• annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the first layer of polycrystalline silicon and having a crystal orientation that is independent from the substrate;
• forming a second transistor plane as a second transistor-based circuit device on the first layer of polycrystalline silicon having the increased grain size, the second circuit device having channels of field effect transistors;
• depositing a second insulator layer on the second transistor plane;
• depositing a second layer of polycrystalline silicon on the second insulator layer;
• and
• annealing the second layer of polycrystalline silicon using laser heating, the laser heating increasing grain size of the second layer of polycrystalline silicon and having a crystal orientation that is independent from the crystal orientation for the first layer of polycrystalline silicon having the increased grain size.