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US 11,114,345 B2Granted
IC including standard cells and SRAM cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
An IC is provided. The IC includes a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs). At least one first P-type GAA FET includes a plurality of silicon (Si) channel regions vertically stacked over an N-type well region. At least one second P-type GAA FET includes a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region.
Claims20
An integrated circuit (IC), comprising:
- a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs), comprising:
- at least one first P-type GAA FET comprising a plurality of silicon (Si) channel regions vertically stacked over an N-type well region;
- and
- at least one second P-type GAA FET comprising a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region;
- at least one SRAM memory cell comprising the first P-type GAA FET;
- and
- at least one standard cell or I/O cell comprising the second P-type GAA FET.
4 more elements
An integrated circuit (IC), comprising:
- a first P-type gate-all-around (GAA) field-effect transistor (FET) comprising a plurality of first silicon (Si) channel regions vertically stacked over a substrate;
- a second P-type GAA FET comprising a plurality of first silicon germanium (SiGe) channel regions vertically stacked over the substrate;
- and
- a third P-type GAA FET comprising a plurality of second SiGe channel regions vertically stacked over the substrate,
- wherein the second SiGe channel regions are surrounded by a first gate electrode,
- wherein a gate dielectric layer is formed between the second SiGe channel regions and the first gate electrode, and the gate dielectric layer comprises Lanthanum-doped (La-doped) dielectric material,
- wherein threshold voltages of the first, second and third P-type GAA FETs are different.
4 more elements
An integrated circuit (IC), comprising:
- a plurality of cells arranged in an array, comprising:
- a first cell, comprising at least one first P-type gate-all-around (GAA) field-effect transistor (FET) having a plurality of silicon (Si) channel regions vertically stacked over an N-type well region;
- a second cell, comprising at least one second P-type GAA FET having a plurality of first silicon germanium (SiGe) channel regions vertically stacked over the N-type well region;
- and
- a third cell, comprising at least one third P-type GAA FET having a plurality of second SiGe channel regions vertically stacked over the N-type well region,
- wherein Ge atomic concentration in the first SiGe channel regions is different from Ge atomic concentration in the second SiGe channel regions.
3 more elements
Dependencies are inferred from the claim text.