US 11,114,337 B2Granted

Method for bonding and interconnecting semiconductor chips

AssigneeImec Vzw

InventorsGaspard Hiblot, Julien Jussot, Geert Van der Plas

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Abstract

A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.

Claims10

Dependent claims

A method of bonding a first semiconductor chip on a first substrate to a second semiconductor chip on a second substrate, comprising:

providing a bonding layer on at least one of the first substrate and the second substrate, the bonding layer being formed of a dielectric bonding material, wherein the dielectric material is Hydrogen Silsesquioxane (HSQ), or an equivalent thereof;
bonding the first substrate to the second substrate and performing a thermal annealing, so as to obtain a stack of the substrates with a bond layer between the first substrate and the second substrate, wherein the first substrate is thinned either before or after the bonding, and wherein the thermal annealing takes place at a temperature below a temperature at which the dielectric bonding material transforms into silicon oxide;
after bonding, scanning an electron beam across an area of the thinned first substrate, an energy of the electron beam being sufficient for the electron beam to reach the bond layer and to transform the scanned dielectric bonding material of the bond layer into a silicon oxide, to thereby obtain a volume of the bond layer that is transformed into a silicon oxide, wherein the volume is essentially a closed wall extending over a full thickness of the bond layer, and enclosing a volume of bonding material, thereby separating that volume of bonding material from the rest of the bond layer;
etching a via opening through the thinned first substrate until reaching an interior of the closed wall, and a dielectric liner is formed on sidewalls of the via opening;
through the via opening, removing the dielectric bonding material from the interior of the closed wall, selectively with respect to the silicon oxide, so as to create a cavity in the bond layer and expose a conductor in the second substrate;
and
filling the cavity and the via opening with an electrically conductive material, to thereby form an electrical connection that connects the conductor in the second substrate to a conductor present in the first substrate and/or to a contact present on top of the stack.

4 more elements

A method of bonding a first semiconductor chip on a first substrate to a second semiconductor chip on a second substrate, comprising:

providing a bonding layer on at least one of the first substrate and the second substrate, the bonding layer being formed of a dielectric material, wherein the dielectric material is Hydrogen Silsesquioxane (HSQ), or an equivalent thereof,
bonding the first substrate to the second substrate, and performing a thermal annealing, so as to obtain a stack of the first substrate and the second substrate with a bond layer between the first substrate and the second substrate, wherein the first substrate is thinned either before or after the bonding, and wherein the thermal annealing takes place at a temperature below a temperature at which the dielectric material transforms into silicon oxide,
after bonding, scanning an electron beam across an area of the thinned first substrate, an energy of the electron beam being sufficient for the electron beam to reach the bond layer and to transform the dielectric material of the bond layer into a silicon oxide, to thereby obtain a volume of the bond layer that is transformed into a silicon oxide, wherein the volume is a solid shape extending over a full thickness of the bond layer;
etching a via opening through the thinned first substrate until reaching the solid shape, and forming a dielectric liner on the sidewalls of the via opening;
removing, through the via opening, the silicon oxide of the solid shape selectively with respect to the dielectric material, so as to create a cavity in the bond layer and expose a conductor in the second substrate;
and
filling the cavity and the via opening with an electrically conductive material, to thereby form an electrical connection that connects the conductor in the second substrate to a conductor in the first substrate and/or to a contact on top of the stack.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/716,025Filed 16 Dec 2019
Priority: EP 1821385219 Dec 2018
Published: US 2020/0203224 A125 Jun 2020
Granted: 7 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10P 90/1914
Preparing SOI wafers: using bonding
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes

Family

US 2020/0203224 A1Pre-grant publication · published 25 Jun 2020
US 11,114,337 B2This patent

From the US filing history. Foreign family members aren’t listed.

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