Memory device for compensating for current of off cells and operating method thereof

A memory device comprising:

• a memory cell array comprising a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect;
• and
• a leakage current compensation circuit connected to a selected word line path from a selected memory cell of the plurality of memory cells to a sense amplifier, and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in a read operation mode of the memory device,
• wherein the leakage current compensation circuit is electrically connected to the selected word line path in a precharge period in which a selected bit line connected to the selected memory cell from among the plurality of bit lines is precharged.

A memory device comprising a plurality of tiles, wherein each of the plurality of tiles comprises:

• a memory cell array comprising a plurality of memory cells connected to intersections between a plurality of word lines and a plurality of bit lines;
• a sense amplifier configured to amplify a voltage difference value between a voltage of a selected word line of the plurality of word lines and a reference voltage, in a read operation mode of the memory device, the selected word line coupled to a selected memory cell of the plurality of memory cells;
• a discharge transistor connected to one end of the sense amplifier and configured to discharge a charge of the selected word line in the read operation mode of the memory device;
• and
• a leakage current compensation circuit coupled to the discharge transistor and configured to compensate for a first current value generated by off cells of the plurality of memory cells in the read operation mode of the memory device, the off cells connected to the selected word line.