Semiconductor memory device including page buffers

A semiconductor memory device comprising:

• a memory cell array defined in a memory structure stacked on a logic structure;
• and
• a page buffer, defined in the logic structure, that includes a sensing circuit that reads data stored in the memory cell array,
• the page buffer comprising:
• a first transistor included in the sensing circuit;
• and
• a second transistor not included in the sensing circuit,
• wherein a cross-sectional dimension of a first contact coupled to the first transistor and a cross-sectional dimension of a second contact coupled to the second transistor are different from each other.

A semiconductor memory device comprising:

• a memory cell array defined in a cell wafer;
• and
• a page buffer, defined in a peripheral wafer bonded onto the cell wafer, that includes a sensing circuit that reads data stored in the memory cell array,
• the page buffer comprising:
• a first transistor included in the sensing circuit;
• and
• a second transistor not included in the sensing circuit,
• wherein a cross-sectional dimension of a first contact coupled to a junction region of the first transistor and a cross-sectional dimension of a second contact coupled to a junction region of the second transistor are different from each other.